To increase device speed, the lengths of gate electrodes are decreasing. At the small dimensions that are currently used, it is important that the gate electrode has straight sidewalls. If the top of the gate electrode is etched more than the bottom, then the small area of the top of the gate electrode makes it difficult to salicide the top of the gate electrode. If, instead, the bottom of the gate electrode is narrower than the top, a shadow effect occurs making it difficult to implant source and drain regions adjacent the gate electrode. The profile of the sidewalls is predominantly determined by etching.
Etching also can create a nonuniformity of the critical dimension of features, such as gate electrodes, across the wafer. For example, the dimension of a feature in one area of the circuit or wafer may be larger than the dimension of another feature in a different area of the wafer even though the two features are intended to have the same dimension. This non-uniformity of dimension can be caused by non-uniformity in the location of neighboring features. This nonuniformity in neighbor feature location is typically most important within 1 to 2 micrometers of the feature with the critical dimension. In addition to affecting the critical dimension of the feature the nonuniformity of neighboring feature location also negatively impacts the final gate profile of the feature. Additionally, variations in gate profiles also affect critical dimensions when the variations affect the bottom portions of the gates.
One proposal for improving the dimension and gate profile uniformity is to have dummy features placed close to, but not in contact with, isolated feature edges. This may be performed manually by placing dummy features having predetermined shapes and dimensions near features. However, this is time consuming and subject to error. In addition, the addition of dummy features may negatively affect pattern density across a wafer, which can negatively impact the depth of focus of photolithography and chemical mechanical processing (CMP). Hence, a fast, robust, and efficient method for placing dummy features that does not negatively impact photolithography or CMP is needed.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.